athn.diff

Stefan Sperling, 03/15/2014 10:02 am

Download (22.4 kB)

ar9003.c 21 Oct 2013 16:20:04 -0000
93 93
int	ar9003_tx_process(struct athn_softc *);
94 94
void	ar9003_tx_intr(struct athn_softc *);
95 95
int	ar9003_swba_intr(struct athn_softc *);
96
void	ar9003_bb_watchdog_intr(struct athn_softc *);
96 97
int	ar9003_intr(struct athn_softc *);
97 98
int	ar9003_tx(struct athn_softc *, struct mbuf *, struct ieee80211_node *,
98 99
	    int);
......
119 120
void	ar9003_next_calib(struct athn_softc *);
120 121
void	ar9003_calib_iq(struct athn_softc *);
121 122
int	ar9003_get_iq_corr(struct athn_softc *, int32_t[], int32_t[]);
122
int	ar9003_calib_tx_iq(struct athn_softc *);
123
int	ar9003_calib_tx_iq_result(struct athn_softc *);
123 124
void	ar9003_paprd_calib(struct athn_softc *, struct ieee80211_channel *);
124 125
int	ar9003_get_desired_txgain(struct athn_softc *, int, int);
125 126
void	ar9003_force_txgain(struct athn_softc *, uint32_t);
......
147 148
void	ar9003_set_cck_weak_signal(struct athn_softc *, int);
148 149
void	ar9003_set_firstep_level(struct athn_softc *, int);
149 150
void	ar9003_set_spur_immunity_level(struct athn_softc *, int);
151
void	ar9003_init_pll(struct athn_softc *);
150 152

  
151 153
/* Extern functions. */
152 154
void	athn_stop(struct ifnet *, int);
......
205 207
	sc->obs_off = AR_OBS;
206 208
	sc->gpio_input_en_off = AR_GPIO_INPUT_EN_VAL;
207 209

  
210
	sc->workaround = AR_READ(sc, AR_WA) |
211
	    AR_WA_ASPM_TIMER_BASED_DISABLE | AR_WA_D3_L1_DISABLE;
212

  
208 213
	if (!(sc->flags & ATHN_FLAG_PCIE))
209 214
		athn_config_nonpcie(sc);
210 215
	else
......
563 568
	AR_SETBITS(sc, AR_GPIO_INPUT_EN_VAL, AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
564 569
	reg = AR_READ(sc, AR_GPIO_INPUT_MUX2);
565 570
	reg = RW(reg, AR_GPIO_INPUT_MUX2_RFSILENT, 0);
571
	reg = RW(reg, AR_GPIO_INPUT_MUX2_RFSILENT, sc->rfsilent_pin);
566 572
	AR_WRITE(sc, AR_GPIO_INPUT_MUX2, reg);
567 573
	ar9003_gpio_config_input(sc, sc->rfsilent_pin);
568 574
	AR_SETBITS(sc, AR_PHY_TEST, AR_PHY_TEST_RFSILENT_BB);
......
1310 1316
}
1311 1317
#endif
1312 1318

  
1319
void
1320
ar9003_bb_watchdog_intr(struct athn_softc *sc)
1321
{
1322
	uint32_t status, reg;
1323
	static int phy_restart_disabled;
1324

  
1325
	status = AR_READ(sc, AR_PHY_PANIC_WD_STATUS);
1326
	AR_WRITE(sc, AR_PHY_PANIC_WD_STATUS,
1327
	    status & ~AR_PHY_PANIC_WD_STATUS_CLR);
1328

  
1329
	if (!phy_restart_disabled &&
1330
	    MS(status, AR_PHY_PANIC_WD_RX_OFDM) == 0xb) {
1331
		/* BB received unsupported frame rate and will hang
1332
		 * if the PHY is restarted. Disable PHY restart. */
1333
		reg = AR_READ(sc, AR_PHY_RESTART);
1334
		reg &= ~AR_PHY_RESTART_ENA;
1335
		AR_WRITE(sc, AR_PHY_RESTART, reg);
1336
		phy_restart_disabled = 1;
1337
	}
1338
}
1339

  
1313 1340
int
1314 1341
ar9003_intr(struct athn_softc *sc)
1315 1342
{
1316 1343
	uint32_t intr, intr2, intr5, sync;
1344
	static int count;
1317 1345

  
1318 1346
	/* Get pending interrupts. */
1319 1347
	intr = AR_READ(sc, AR_INTR_ASYNC_CAUSE);
1348
	if (count < 4)
1349
		printf("%s: AR_INTR_ASYNC_CAUSE=0x%x\n", __func__, intr);
1320 1350
	if (!(intr & AR_INTR_MAC_IRQ) || intr == AR_INTR_SPURIOUS) {
1321 1351
		intr = AR_READ(sc, AR_INTR_SYNC_CAUSE);
1322 1352
		if (intr == AR_INTR_SPURIOUS || (intr & sc->isync) == 0)
......
1324 1354
	}
1325 1355

  
1326 1356
	if ((AR_READ(sc, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) &&
1327
	    (AR_READ(sc, AR_RTC_STATUS) & AR_RTC_STATUS_M) == AR_RTC_STATUS_ON)
1357
	    (AR_READ(sc, AR_RTC_STATUS) & AR_RTC_STATUS_M) == AR_RTC_STATUS_ON) {
1328 1358
		intr = AR_READ(sc, AR_ISR);
1329
	else
1359
		if (count < 4)
1360
			printf("%s: AR_ISR=0x%x\n", __func__, intr);
1361
	} else
1330 1362
		intr = 0;
1331 1363
	sync = AR_READ(sc, AR_INTR_SYNC_CAUSE) & sc->isync;
1364
	if (count < 4)
1365
		printf("%s: AR_INTR_SYNC_CAUSE=0x%x\n", __func__, sync);
1332 1366
	if (intr == 0 && sync == 0)
1333 1367
		return (0);	/* Not for us. */
1334 1368

  
1335 1369
	if (intr != 0) {
1336 1370
		if (intr & AR_ISR_BCNMISC) {
1337 1371
			intr2 = AR_READ(sc, AR_ISR_S2);
1372
			if (count < 4)
1373
				printf("%s: AR_ISR_S2=0x%x\n", __func__, intr2);
1338 1374
			if (intr2 & AR_ISR_S2_TIM)
1339 1375
				/* TBD */;
1340 1376
			if (intr2 & AR_ISR_S2_TSFOOR)
1341 1377
				/* TBD */;
1342 1378
			if (intr2 & AR_ISR_S2_BB_WATCHDOG)
1343
				/* TBD */;
1379
				ar9003_bb_watchdog_intr(sc);
1344 1380
		}
1345 1381
		intr = AR_READ(sc, AR_ISR_RAC);
1382
		if (count < 4)
1383
			printf("%s: AR_ISR_RAC=0x%x\n", __func__, intr);
1346 1384
		if (intr == AR_INTR_SPURIOUS)
1347 1385
			return (1);
1348 1386

  
......
1369 1407
			    MS(intr5, AR_ISR_S5_GENTIMER_THRESH)));
1370 1408
		}
1371 1409
	}
1410
	count++;
1372 1411
	if (sync != 0) {
1373 1412
		if (sync & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
1374 1413
			AR_WRITE(sc, AR_RC, AR_RC_HOSTIF);
......
2069 2108
	AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
2070 2109
}
2071 2110

  
2111
#define DELPT	32
2072 2112
int
2073 2113
ar9003_init_calib(struct athn_softc *sc)
2074 2114
{
2075 2115
	uint8_t txchainmask, rxchainmask;
2076 2116
	uint32_t reg;
2077
	int ntries;
2117
	int ntries, error;
2078 2118

  
2079 2119
	/* Save chains masks. */
2080 2120
	txchainmask = sc->txchainmask;
2081 2121
	rxchainmask = sc->rxchainmask;
2082 2122
	/* Configure hardware before calibration. */
2083
	if (AR_READ(sc, AR_ENT_OTP) & AR_ENT_OTP_CHAIN2_DISABLE)
2084
		txchainmask = rxchainmask = 0x3;
2085
	else
2086
		txchainmask = rxchainmask = 0x7;
2123
	if (!AR_SREV_9485_OR_LATER(sc)) {
2124
		if (AR_READ(sc, AR_ENT_OTP) & AR_ENT_OTP_CHAIN2_DISABLE)
2125
			txchainmask = rxchainmask = 0x3;
2126
		else
2127
			txchainmask = rxchainmask = 0x7;
2128
	}
2087 2129
	ar9003_init_chains(sc);
2088 2130

  
2089 2131
	/* Perform Tx IQ calibration. */
2090
	ar9003_calib_tx_iq(sc);
2091
	/* Disable and re-enable the PHY chips. */
2092
	AR_WRITE(sc, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
2093
	AR_WRITE_BARRIER(sc);
2094
	DELAY(5);
2095
	AR_WRITE(sc, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
2132
	reg = AR_READ(sc, AR_PHY_TX_IQCAL_CONTROL_1);
2133
	reg = RW(reg, AR_PHY_TX_IQCAQL_CONTROL_1_IQCORR_I_Q_COFF_DELPT, DELPT);
2134
	AR_WRITE(sc, AR_PHY_TX_IQCAL_CONTROL_1, reg);
2135

  
2136
	/* 
2137
	 * For AR9485 or later chips, TxIQ cal runs as part of
2138
	 * AGC calibration.
2139
	 */
2140
	if (AR_SREV_9485_OR_LATER(sc)) {
2141
		AR_CLRBITS(sc, AR_PHY_TX_IQCAL_CONTROL_0,
2142
		    AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL);
2143

  
2144
		/* Disable calibrations we don't (yet?) support. */
2145
		AR_CLRBITS(sc, AR_PHY_AGC_CONTROL,
2146
		   AR_PHY_AGC_CONTROL_OFFSET_CAL |
2147
		   AR_PHY_AGC_CONTROL_FLTR_CAL |
2148
		   AR_PHY_AGC_CONTROL_PKDET_CAL);
2149
	} else {
2150
		/* Start Tx IQ calibration. */
2151
		AR_SETBITS(sc, AR_PHY_TX_IQCAL_START,
2152
		    AR_PHY_TX_IQCAL_START_DO_CAL);
2153
		/* Wait for completion. */
2154
		for (ntries = 0; ntries < 10000; ntries++) {
2155
			reg = AR_READ(sc, AR_PHY_TX_IQCAL_START);
2156
			if (!(reg & AR_PHY_TX_IQCAL_START_DO_CAL))
2157
				break;
2158
			DELAY(10);
2159
		}
2160
		if (ntries == 10000)
2161
			return (ETIMEDOUT);
2162

  
2163
		error = ar9003_calib_tx_iq_result(sc);
2164
		if (error)
2165
			return (error);
2166

  
2167
		/* Disable and re-enable the PHY chips. */
2168
		AR_WRITE(sc, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
2169
		AR_WRITE_BARRIER(sc);
2170
		DELAY(5);
2171
		AR_WRITE(sc, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
2172
	}
2096 2173

  
2097 2174
	/* Calibrate the AGC. */
2098 2175
	AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
......
2106 2183
	if (ntries == 10000)
2107 2184
		return (ETIMEDOUT);
2108 2185

  
2186
	if (AR_SREV_9485_OR_LATER(sc)) {
2187
		error = ar9003_calib_tx_iq_result(sc);
2188
		if (error)
2189
			return (error);
2190
	}
2191

  
2109 2192
	/* Restore chains masks. */
2110 2193
	sc->txchainmask = txchainmask;
2111 2194
	sc->rxchainmask = rxchainmask;
......
2213 2296
	memset(&sc->calib, 0, sizeof(sc->calib));
2214 2297
}
2215 2298

  
2216
#define DELPT	32
2217 2299
int
2218 2300
ar9003_get_iq_corr(struct athn_softc *sc, int32_t res[6], int32_t coeff[2])
2219 2301
{
......
2334 2416
}
2335 2417

  
2336 2418
int
2337
ar9003_calib_tx_iq(struct athn_softc *sc)
2419
ar9003_calib_tx_iq_result(struct athn_softc *sc)
2338 2420
{
2339 2421
	uint32_t reg;
2340 2422
	int32_t res[6], coeff[2];
2341
	int i, j, ntries;
2342

  
2343
	reg = AR_READ(sc, AR_PHY_TX_IQCAL_CONTROL_1);
2344
	reg = RW(reg, AR_PHY_TX_IQCAQL_CONTROL_1_IQCORR_I_Q_COFF_DELPT, DELPT);
2345
	AR_WRITE(sc, AR_PHY_TX_IQCAL_CONTROL_1, reg);
2346

  
2347
	/* Start Tx IQ calibration. */
2348
	AR_SETBITS(sc, AR_PHY_TX_IQCAL_START, AR_PHY_TX_IQCAL_START_DO_CAL);
2349
	/* Wait for completion. */
2350
	for (ntries = 0; ntries < 10000; ntries++) {
2351
		reg = AR_READ(sc, AR_PHY_TX_IQCAL_START);
2352
		if (!(reg & AR_PHY_TX_IQCAL_START_DO_CAL))
2353
			break;
2354
		DELAY(10);
2355
	}
2356
	if (ntries == 10000)
2357
		return (ETIMEDOUT);
2423
	int i, j;
2358 2424

  
2359 2425
	for (i = 0; i < sc->ntxchains; i++) {
2360 2426
		/* Read Tx IQ calibration status for this chain. */
......
2363 2429
			return (EIO);
2364 2430
		/*
2365 2431
		 * Read Tx IQ calibration results for this chain.
2366
		 * This consists in twelve signed 12-bit values.
2432
		 * Results consist of twelve signed 12-bit values.
2367 2433
		 */
2368 2434
		for (j = 0; j < 3; j++) {
2369 2435
			AR_CLRBITS(sc, AR_PHY_CHAN_INFO_MEMORY,
......
3193 3259
	ar9003_set_phy(sc, c, extc);
3194 3260
	ar9003_init_chains(sc);
3195 3261

  
3262
	if (AR_SREV_9380_20_OR_LATER(sc)) {
3263
		/* Enable BB watchdog interrupt. */
3264
		reg = AR_READ(sc, AR_PHY_PANIC_WD_CTL_2);
3265
		reg |= AR_PHY_PANIC_WD_IRQ_ENABLE;
3266
		reg &= ~AR_PHY_PANIC_WD_RST_ENABLE;
3267
		AR_WRITE(sc, AR_PHY_PANIC_WD_CTL_2, reg);
3268

  
3269
		/*
3270
		 * Enable watchdog in non-IDLE mode, disable in IDLE mode,
3271
		 * set idle timeout to 25ms.
3272
		 */
3273
		AR_WRITE(sc, AR_PHY_PANIC_WD_CTL_1,
3274
		    AR_PHY_PANIC_WD_NON_IDLE_ENABLE |
3275
		    AR_PHY_PANIC_WD_IDLE_MASK |
3276
		    ((AR_PHY_PANIC_WD_NON_IDLE_MASK) & ((100 * 25) / 74) << 2));
3277
	}
3278

  
3196 3279
	ops->set_txpower(sc, c, extc);
3197 3280
#undef X
3198 3281
}
......
3374 3457
	reg = RW(reg, AR_PHY_TIMING5_CYCPWR_THR1, (level + 1) * 2);
3375 3458
	AR_WRITE(sc, AR_PHY_TIMING5, reg);
3376 3459
	AR_WRITE_BARRIER(sc);
3460
}
3461

  
3462

  
3463
void
3464
ar9003_init_pll(struct athn_softc *sc)
3465
{
3466
	uint32_t reg;
3467

  
3468
	if (AR_SREV_9485(sc)) {
3469
		reg = AR_READ(sc, AR_PHY_65NM_CH0_DPLL2);
3470
		reg = RW(reg, AR_PHY_65NM_CH0_DPLL2_PLL_PWD, 0x01);
3471
		AR_WRITE(sc, AR_PHY_65NM_CH0_DPLL2, reg);
3472

  
3473
		/* program BB PLL ki and kd value, ki=0x4, kd=0x40 */
3474
		reg = RW(reg, AR_PHY_65NM_CH0_DPLL2_KD, 0x40);
3475
		reg = RW(reg, AR_PHY_65NM_CH0_DPLL2_KI, 0x04);
3476
		AR_WRITE(sc, AR_PHY_65NM_CH0_DPLL2, reg);
3477

  
3478
		reg = AR_READ(sc, AR_PHY_65NM_CH0_DPLL1);
3479
		reg = RW(reg, AR_PHY_65NM_CH0_DPLL1_REFDIV, 0x05);
3480
		reg = RW(reg, AR_PHY_65NM_CH0_DPLL1_NINI, 0x58);
3481
		reg = RW(reg, AR_PHY_65NM_CH0_DPLL1_NFRAC, 0x00);
3482
		AR_WRITE(sc, AR_PHY_65NM_CH0_DPLL1, reg);
3483

  
3484
		reg = AR_READ(sc, AR_PHY_65NM_CH0_DPLL2);
3485
		reg = RW(reg, AR_PHY_65NM_CH0_DPLL2_OUTDIV, 0x01);
3486
		reg = RW(reg, AR_PHY_65NM_CH0_DPLL2_LOCAL_PLL, 0x01);
3487
		reg = RW(reg, AR_PHY_65NM_CH0_DPLL2_NEGTRIG, 0x01);
3488
		AR_WRITE(sc, AR_PHY_65NM_CH0_DPLL2, reg);
3489

  
3490
		/* program BB PLL phase_shift to 0x6 */
3491
		reg = AR_READ(sc, AR_PHY_65NM_CH0_DPLL3);
3492
		reg = RW(reg, AR_PHY_65NM_CH0_DPLL3_PHASE_SHIFT, 0x06);
3493
		AR_WRITE(sc, AR_PHY_65NM_CH0_DPLL3, reg);
3494
		
3495
		reg = AR_READ(sc, AR_PHY_65NM_CH0_DPLL2);
3496
		reg = RW(reg, AR_PHY_65NM_CH0_DPLL2_PLL_PWD, 0x00);
3497
		AR_WRITE(sc, AR_PHY_65NM_CH0_DPLL2, reg);
3498

  
3499
		AR_WRITE_BARRIER(sc);
3500
		DELAY(1000);
3501
	}
3377 3502
}
ar9003reg.h 2 Oct 2013 14:53:41 -0000
198 198
#define AR_PHY_TX_FORCED_GAIN		0x0a458
199 199
#define AR_PHY_PDADC_TAB(i)		(0x0a480 + (i) * 0x1000)
200 200
#define AR_PHY_TXGAIN_TABLE(i)		(0x0a500 + (i) * 4)
201
#define AR_PHY_TX_IQCAL_CONTROL_1	0x0a648
202
#define AR_PHY_TX_IQCAL_START		0x0a640
203
#define AR_PHY_TX_IQCAL_CORR_COEFF_01_B(i)	\
204
					(0x0a650 + (i) * 0x1000)
205
#define AR_PHY_TX_IQCAL_STATUS_B(i)	(0x0a68c + (i) * 0x1000)
206
#define AR_PHY_PAPRD_TRAINER_CNTL1	0x0a690
207
#define AR_PHY_PAPRD_TRAINER_CNTL2	0x0a694
208
#define AR_PHY_PAPRD_TRAINER_CNTL3	0x0a698
209
#define AR_PHY_PAPRD_TRAINER_CNTL4	0x0a69c
201
#define AR_PHY_TX_IQCAL_CONTROL_0   	(AR_SREV_9485(sc) ? 0x0a5c4 : 0x0a644)
202
#define AR_PHY_TX_IQCAL_CONTROL_1	(AR_SREV_9485(sc) ? 0x0a5c8 : 0x0a648)
203
#define AR_PHY_TX_IQCAL_START		(AR_SREV_9485(sc) ? 0x0a5c4 : 0x0a640)
204
#define AR_PHY_TX_IQCAL_CORR_COEFF_01_B( i)	\
205
					(AR_SREV_9485(sc) \
206
					    ? (0x0a5d0 + (i) * 0x1000) \
207
					    : (0x0a650 + (i) * 0x1000))
208
#define AR_PHY_TX_IQCAL_STATUS_B(i)	(AR_SREV_9485(sc) \
209
					    ? (0x0a5f0 + (i) * 0x1000) \
210
					    : (0x0a68c + (i) * 0x1000))
211
#define AR_PHY_PAPRD_TRAINER_CNTL1	(AR_SREV_9485(sc) ? 0xa780 : 0x0a690)
212
#define AR_PHY_PAPRD_TRAINER_CNTL2	(AR_SREV_9485(sc) ? 0xa784 : 0x0a694)
213
#define AR_PHY_PAPRD_TRAINER_CNTL3	(AR_SREV_9485(sc) ? 0xa788 : 0x0a698)
214
#define AR_PHY_PAPRD_TRAINER_CNTL4	(AR_SREV_9485(sc) ? 0xa78c : 0x0a69c)
210 215
#define AR_PHY_PAPRD_TRAINER_STAT1	0x0a6a0
211 216
#define AR_PHY_PAPRD_TRAINER_STAT2	0x0a6a4
212 217
#define AR_PHY_PAPRD_TRAINER_STAT3	0x0a6a8
......
218 223
#define AR_PHY_ONLY_CTL			0x0a7d4
219 224
#define AR_PHY_ECO_CTRL			0x0a7dc
220 225

  
226
/* Bits for AR_PHY_PANIC_WD_STATUS. */
227
#define AR_PHY_PANIC_WD_STATUS_CLR	0x00000008	
228
#define AR_PHY_PANIC_WD_INFO		0x00000007
229
#define AR_PHY_PANIC_WD_INFO_S		0
230
#define AR_PHY_PANIC_WD_DET_HANG	0x00000008
231
#define AR_PHY_PANIC_WD_DET_HANG_S	3
232
#define AR_PHY_PANIC_WD_RADAR_M		0x000000f0
233
#define AR_PHY_PANIC_WD_RADAR_S		4
234
#define AR_PHY_PANIC_WD_RX_OFDM_M	0x00000f00
235
#define AR_PHY_PANIC_WD_RX_OFDM_S	8
236
#define AR_PHY_PANIC_WD_RX_CCK_M	0x0000f000
237
#define AR_PHY_PANIC_WD_RX_CCK_S	12
238
#define AR_PHY_PANIC_WD_TX_OFDM_M	0x000f0000
239
#define AR_PHY_PANIC_WD_TX_OFDM_S	16
240
#define AR_PHY_PANIC_WD_TX_CCK_M	0x00f00000
241
#define AR_PHY_PANIC_WD_TX_CCK_S	20
242
#define AR_PHY_PANIC_WD_AGC_M		0x0f000000
243
#define AR_PHY_PANIC_WD_AGC_S		24
244
#define AR_PHY_PANIC_WD_SRCH_M		0Xf0000000
245
#define AR_PHY_PANIC_WD_SRCH_S		28
246

  
247

  
248
/* Bits for AR_PHY_PANIC_WD_CTL_1. */
249
#define AR_PHY_PANIC_WD_NON_IDLE_ENABLE	0x00000001
250
#define AR_PHY_PANIC_WD_IDLE_ENABLE	0x00000002
251
#define AR_PHY_PANIC_WD_IDLE_MASK	0Xffff0000
252
#define AR_PHY_PANIC_WD_NON_IDLE_MASK	0x0000fffc
253

  
254
/* Bits for AR_PHY_PANIC_WD_CTL_2. */
255
#define AR_PHY_PANIC_WD_RST_ENABLE	0x00000002
256
#define AR_PHY_PANIC_WD_IRQ_ENABLE	0x00000004
257
#define AR_PHY_PANIC_WD_CNTL2_MASK	0Xfffffff9
258

  
221 259
/*
222 260
 * Analog registers.
223 261
 */
......
230 268
#define AR_PHY_65NM_CH0_RXTX1		0x16100
231 269
#define AR_PHY_65NM_CH0_RXTX2		0x16104
232 270
#define AR_PHY_65NM_CH0_RXTX4		0x1610c
271
#define AR_PHY_65NM_CH0_DPLL1		0x16180
272
#define AR_PHY_65NM_CH0_DPLL2		0x16184
273
#define AR_PHY_65NM_CH0_DPLL3		0x16188
233 274
#define AR9485_PHY_65NM_CH0_TOP2	0x16284
234 275
#define AR_PHY_65NM_CH0_TOP		0x16288
235
#define AR_PHY_65NM_CH0_THERM		0x16290
276
#define AR_PHY_65NM_CH0_THERM		(AR_SREV_9485(sc) ? 0x1628c : 0x16290)
236 277
#define AR9485_PHY_CH0_XTAL		0x16290
237 278
#define AR_PHY_65NM_CH1_RXTX1		0x16500
238 279
#define AR_PHY_65NM_CH1_RXTX2		0x16504
......
620 661
#define AR_PHY_AGC_CONTROL_NO_UPDATE_NF		0x00020000
621 662
#define AR_PHY_AGC_CONTROL_EXT_NF_PWR_MEAS	0x00040000
622 663
#define AR_PHY_AGC_CONTROL_CLC_SUCCESS		0x00080000
664
#define AR_PHY_AGC_CONTROL_PKDET_CAL		0x00100000
623 665

  
624 666
/* Bits for AR_PHY_CALMODE. */
625 667
#define AR_PHY_CALMODE_IQ		0x00000000
......
765 807
#define AR_PHY_TXGAIN_INDEX_M		0xff000000
766 808
#define AR_PHY_TXGAIN_INDEX_S		24
767 809

  
810
/* Bits for AR_PHY_TX_IQCAL_CONTROL_0. */
811
#define AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL		0x80000000
812

  
768 813
/* Bits for AR_PHY_TX_IQCAL_CONTROL_1. */
769 814
#define AR_PHY_TX_IQCAQL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_M	0x01fc0000
770 815
#define AR_PHY_TX_IQCAQL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_S	18
......
886 931

  
887 932
/* Bits for AR_PHY_65NM_CH0_RXTX4. */
888 933
#define AR_PHY_65NM_CH0_RXTX4_THERM_ON  0x10000000
934

  
935
/* Bits for AR_PHY_65NM_CH0_DPLL1. */
936
#define AR_PHY_65NM_CH0_DPLL1_REFDIV_M	0xf8000000
937
#define AR_PHY_65NM_CH0_DPLL1_REFDIV_S	27
938
#define AR_PHY_65NM_CH0_DPLL1_NINI_M	0X07fc0000
939
#define AR_PHY_65NM_CH0_DPLL1_NINI_S	18
940
#define AR_PHY_65NM_CH0_DPLL1_NFRAC_M	0X0003ffff
941
#define AR_PHY_65NM_CH0_DPLL1_NFRAC_S	0
942

  
943
/* Bits for AR_PHY_65NM_CH0_DPLL2. */
944
#define AR_PHY_65NM_CH0_DPLL2_LOCAL_PLL_M	0x40000000
945
#define AR_PHY_65NM_CH0_DPLL2_LOCAL_PLL_S	30
946
#define AR_PHY_65NM_CH0_DPLL2_KI_M		0x3c000000
947
#define AR_PHY_65NM_CH0_DPLL2_KI_S		26
948
#define AR_PHY_65NM_CH0_DPLL2_KD_M		0x03f80000
949
#define AR_PHY_65NM_CH0_DPLL2_KD_S		19
950
#define AR_PHY_65NM_CH0_DPLL2_NEGTRIG_M		0x00040000
951
#define AR_PHY_65NM_CH0_DPLL2_NEGTRIG_S		18
952
#define AR_PHY_65NM_CH0_DPLL2_PLL_PWD_M		0x00010000
953
#define AR_PHY_65NM_CH0_DPLL2_PLL_PWD_S		16
954
#define AR_PHY_65NM_CH0_DPLL2_OUTDIV_M		0x0000e000
955
#define AR_PHY_65NM_CH0_DPLL2_OUTDIV_S		13
956

  
957
/* Bits for AR_PHY_65NM_CH0_DPLL3. */
958
#define AR_PHY_65NM_CH0_DPLL3_PHASE_SHIFT_M	0x3f800000
959
#define AR_PHY_65NM_CH0_DPLL3_PHASE_SHIFT_S	23
889 960

  
890 961
/* Bits for AR9485_PHY_65NM_CH0_TOP2. */
891 962
#define AR9485_PHY_65NM_CH0_TOP2_XPABIASLVL_M	0x0000f000
ar9380.c 18 Oct 2013 19:48:03 -0000
220 220
	struct ar9380_eeprom *eep = sc->eep;
221 221
	struct ar9380_base_eep_hdr *base = &eep->baseEepHeader;
222 222
	struct ar9380_modal_eep_header *modal;
223
	int i;
223
	int i, maxchains;
224 224

  
225 225
	base->regDmn[0] = swap16(base->regDmn[0]);
226 226
	base->regDmn[1] = swap16(base->regDmn[1]);
......
231 231
	modal->antCtrlCommon2 = swap32(modal->antCtrlCommon2);
232 232
	modal->papdRateMaskHt20 = swap32(modal->papdRateMaskHt20);
233 233
	modal->papdRateMaskHt40 = swap32(modal->papdRateMaskHt40);
234
	for (i = 0; i < AR9380_MAX_CHAINS; i++)
234
	maxchains = AR_SREV_9485(sc) ? 1 : AR9380_MAX_CHAINS;
235
	for (i = 0; i < maxchains; i++)
235 236
		modal->antCtrlChain[i] = swap16(modal->antCtrlChain[i]);
236 237

  
237 238
	modal = &eep->modalHeader5G;
......
239 240
	modal->antCtrlCommon2 = swap32(modal->antCtrlCommon2);
240 241
	modal->papdRateMaskHt20 = swap32(modal->papdRateMaskHt20);
241 242
	modal->papdRateMaskHt40 = swap32(modal->papdRateMaskHt40);
242
	for (i = 0; i < AR9380_MAX_CHAINS; i++)
243
	for (i = 0; i < maxchains; i++)
243 244
		modal->antCtrlChain[i] = swap16(modal->antCtrlChain[i]);
244 245
#endif
245 246
}
......
264 265
    struct ieee80211_channel *extc)
265 266
{
266 267
	uint32_t freq = c->ic_freq;
267
	uint32_t chansel, phy;
268
	uint32_t chansel, chanfrac, phy;
268 269

  
269 270
	if (IEEE80211_IS_CHAN_2GHZ(c)) {
270
		if (AR_SREV_9485(sc))
271
			chansel = ((freq << 16) - 215) / 15;
272
		else
271
		if (AR_SREV_9485(sc)) {
272
			chansel = (freq * 4) / 120;
273
			chanfrac = (((freq * 4) % 120) * 0x20000) / 120;
274
			chansel = (chansel << 17) | (chanfrac);
275
		} else {
276
			/* XXX not valid for >= AR_SREV_9330 */
273 277
			chansel = (freq << 16) / 15;
278
		}
274 279
		AR_WRITE(sc, AR_PHY_SYNTH_CONTROL, AR9380_BMODE);
275 280
	} else {
276 281
		chansel = (freq << 15) / 15;
......
848 853
	const struct ar9380_modal_eep_header *modal;
849 854
	uint32_t reg;
850 855
	int8_t slope;
851
	int i, corr, temp, temp0;
856
	int i, corr, temp, temp0, maxchains;
852 857

  
853 858
	if (IEEE80211_IS_CHAN_2GHZ(c))
854 859
		modal = &eep->modalHeader2G;
855 860
	else
856 861
		modal = &eep->modalHeader5G;
857 862

  
858
	for (i = 0; i < AR9380_MAX_CHAINS; i++) {
863
	maxchains = AR_SREV_9485(sc) ? 1 : AR9380_MAX_CHAINS;
864
	for (i = 0; i < maxchains; i++) {
859 865
		ar9380_get_correction(sc, c, i, &corr, &temp);
860 866
		if (i == 0)
861 867
			temp0 = temp;
athn.c 19 Jan 2014 14:54:54 -0000
63 63
#include <dev/ic/athnvar.h>
64 64

  
65 65
#ifdef ATHN_DEBUG
66
int athn_debug = 0;
66
int athn_debug = 2;
67 67
#endif
68 68

  
69 69
void		athn_radiotap_attach(struct athn_softc *);
......
163 163
void		ar9287_1_3_enable_async_fifo(struct athn_softc *);
164 164
void		ar9287_1_3_setup_async_fifo(struct athn_softc *);
165 165
void		ar9003_reset_txsring(struct athn_softc *);
166
void		ar9003_init_pll(struct athn_softc *);
166 167

  
167 168
struct cfdriver athn_cd = {
168 169
	NULL, "athn", DV_IFNET
......
732 733
	uint32_t pll;
733 734

  
734 735
	if (AR_SREV_9380_10_OR_LATER(sc)) {
735
		if (AR_SREV_9485(sc))
736
			AR_WRITE(sc, AR_RTC_PLL_CONTROL2, 0x886666);
736
		ar9003_init_pll(sc);
737 737
		pll = SM(AR_RTC_9160_PLL_REFDIV, 0x5);
738 738
		pll |= SM(AR_RTC_9160_PLL_DIV, 0x2c);
739 739
	} else if (AR_SREV_9280_10_OR_LATER(sc)) {
......
2243 2243
	/* Initialize interrupt mask. */
2244 2244
	sc->imask =
2245 2245
	    AR_IMR_TXDESC | AR_IMR_TXEOL |
2246
	    AR_IMR_RXERR | AR_IMR_RXEOL | AR_IMR_RXORN |
2246
	    AR_IMR_RXERR | AR_IMR_RXORN |
2247 2247
	    AR_IMR_RXMINTR | AR_IMR_RXINTM |
2248 2248
	    AR_IMR_GENTMR | AR_IMR_BCNMISC;
2249 2249
	if (AR_SREV_9380_10_OR_LATER(sc))
......
2288 2288
	ops->init_baseband(sc);
2289 2289

  
2290 2290
	if ((error = athn_init_calib(sc, c, extc)) != 0) {
2291
		printf("%s: could not initialize calibration\n",
2292
		    sc->sc_dev.dv_xname);
2291
		printf("%s: could not initialize calibration (error %d)\n",
2292
		    sc->sc_dev.dv_xname, error);
2293 2293
		return (error);
2294 2294
	}
2295 2295

  
athnreg.h 20 Oct 2013 19:48:17 -0000
253 253

  
254 254

  
255 255
/* Bits for AR_CR. */
256
#define AR_CR_RXE	0x00000004
256
#define AR_CR_RXE	(AR_SREV_9380_20_OR_LATER(sc) ? 0x000c : 0x0004)
257 257
#define AR_CR_RXD	0x00000020
258 258
#define AR_CR_SWI	0x00000040
259 259

  
......
722 722
#define AR5416_WA_DEFAULT	0x0000073f
723 723
#define AR9280_WA_DEFAULT	0x0040073b
724 724
#define AR9285_WA_DEFAULT	0x004a050b
725
#define AR_WA_UNTIE_RESET_EN	0x00008000
726
#define AR_WA_RESET_EN		0x00040000
727
#define AR_WA_ANALOG_SHIFT	0x00100000
728
#define AR_WA_POR_SHORT		0x00200000
725
#define AR_WA_ASPM_TIMER_BASED_DISABLE 	0x00002000
726
#define AR_WA_D3_L1_DISABLE		0x00004000
727
#define AR_WA_UNTIE_RESET_EN		0x00008000
728
#define AR_WA_RESET_EN			0x00040000
729
#define AR_WA_ANALOG_SHIFT		0x00100000
730
#define AR_WA_POR_SHORT			0x00200000
729 731

  
730 732
/* Bits for AR_PM_STATE. */
731 733
#define AR_PM_STATE_PME_D3COLD_VAUX	0x00100000
......
1415 1417

  
1416 1418
#define AR_SREV_9485(sc) \
1417 1419
	((sc)->mac_ver == AR_SREV_VERSION_9485)
1420
#define AR_SREV_9485_OR_LATER(sc) \
1421
	((sc)->mac_ver >= AR_SREV_VERSION_9485)
1418 1422

  
1419 1423
#define AR_SINGLE_CHIP(sc)	AR_SREV_9280_10_OR_LATER(sc)
1420 1424

  
athnvar.h 19 Jan 2014 14:54:54 -0000
20 20
#define ATHN_BT_COEXISTENCE	1
21 21
#endif
22 22

  
23
#define ATHN_DEBUG
24

  
23 25
#ifdef ATHN_DEBUG
24 26
#define DPRINTF(x)	do { if (athn_debug > 0) printf x; } while (0)
25 27
#define DPRINTFN(n, x)	do { if (athn_debug >= (n)) printf x; } while (0)