ath-wip.diff

work-in-progress diff - Stefan Sperling, 07/10/2014 10:50 pm

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ar5212.c 10 Jul 2014 20:49:40 -0000
733 733
	    ee->ee_tx_end2xlna_enable[ee_mode] << 8, 0xffff00ff);
734 734
	AR5K_REG_MASKED_BITS(AR5K_AR5212_PHY(0x19),
735 735
	    (ee->ee_thr_62[ee_mode] << 12) & 0x7f000, 0xfff80fff);
736
	AR5K_REG_MASKED_BITS(AR5K_AR5212_PHY(0x49), 4, 0xffffff01);
736

  
737
	if (ee->ee_version < AR5K_EEPROM_VERSION_3_3) {
738
		AR5K_REG_MASKED_BITS(AR5K_AR5212_PHY(0x49), 4, 0xffffff01);
739
	} else {
740
		/*
741
		 * False detect backoff - suspected 32 MHz spur causes false
742
		 * detects in OFDM, causing Tx Hangs.  Decrease weak signal
743
		 * sensitivity for this card.
744
		 */
745
		u_int32_t clk_freq;
746
		
747
		if (hal->ah_version == AR5K_SREV_VER_AR5413 ||
748
		    hal->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112)
749
			clk_freq = 40;
750
		else
751
			clk_freq = 32;
752

  
753
		printf("%s:clk_freq=%d channel->c_channel=%d\n", __func__, clk_freq, channel->c_channel);
754
		if (((channel->c_channel % clk_freq) != 0) &&
755
		    (((channel->c_channel % clk_freq) < 10) ||
756
		    ((channel->c_channel % clk_freq) > 22))) {
757
			printf("%s:false detect\n", __func__);
758
			AR5K_REG_MASKED_BITS(AR5K_AR5212_PHY(0x49),
759
			    (((2 + ee->ee_false_detect[ee_mode]) << 1) & 0xfe),
760
			    0xffffff01);
761
		}
762
	}
737 763

  
738 764
	AR5K_REG_ENABLE_BITS(AR5K_AR5212_PHY_IQ,
739 765
	    AR5K_AR5212_PHY_IQ_CORR_ENABLE |
......
795 821

  
796 822
	AR5K_DELAY(100 + data);
797 823

  
824
	data = AR5K_REG_READ(AR5K_AR5212_PHY_AGC);
825
	AR5K_REG_WRITE(AR5K_AR5212_PHY_AGC, AR5K_AR5212_PHY_TESTCTRL_TXHOLD);
826
	i = 0;
827
	while ((i++ < 20) &&
828
	    (AR5K_REG_READ(0x9c24) & 0x10)) /* test if baseband not ready */
829
		DELAY(200);
830
	AR5K_REG_WRITE(AR5K_AR5212_PHY_AGC, data);
831
	if (i >= 20) {
832
		AR5K_PRINT("baseband timeout\n");
833
		return (AH_FALSE);
834
	}
835

  
798 836
	/*
799 837
	 * Start calibration
800 838
	 */
......
2889 2927

  
2890 2928
		if (b)
2891 2929
			hal->ah_capabilities.cap_mode |= HAL_MODE_11B;
2892
#if 0
2893 2930
		if (g)
2894 2931
			hal->ah_capabilities.cap_mode |= HAL_MODE_11G;
2895
#endif
2896 2932
	}
2897 2933

  
2898 2934
	/* GPIO */
ar5212reg.h 10 Jul 2014 20:49:40 -0000
1051 1051
 */
1052 1052
#define	AR5K_AR5212_PHY_AGC		0x9808
1053 1053
#define	AR5K_AR5212_PHY_AGC_DISABLE	0x08000000
1054
#define	AR5K_AR5212_PHY_TESTCTRL_TXHOLD	0x00003800 
1055

  
1054 1056

  
1055 1057
/*
1056 1058
 * PHY timing register
ar5xxx.c 10 Jul 2014 20:49:40 -0000
2 2

  
3 3
/*
4 4
 * Copyright (c) 2004, 2005, 2006, 2007 Reyk Floeter <reyk@openbsd.org>
5
 * Copyright (c) 2008 Nick Kossifidis <mick@madwifi.org>
5 6
 *
6 7
 * Permission to use, copy, modify, and distribute this software for any
7 8
 * purpose with or without fee is hereby granted, provided that the above
......
87 88
HAL_BOOL	 ar5k_ar5111_channel(struct ath_hal *, HAL_CHANNEL *);
88 89
HAL_BOOL	 ar5k_ar5111_chan2athchan(u_int, struct ar5k_athchan_2ghz *);
89 90
HAL_BOOL	 ar5k_ar5112_channel(struct ath_hal *, HAL_CHANNEL *);
91
HAL_BOOL	 ar5k_ar2425_channel(struct ath_hal *, HAL_CHANNEL *);
90 92
HAL_BOOL	 ar5k_check_channel(struct ath_hal *, u_int16_t, u_int flags);
91 93

  
92 94
HAL_BOOL	 ar5k_ar5111_rfregs(struct ath_hal *, HAL_CHANNEL *, u_int);
......
1129 1131
		ret = ar5k_ar5110_channel(hal, channel);
1130 1132
	else if (hal->ah_radio == AR5K_AR5111)
1131 1133
		ret = ar5k_ar5111_channel(hal, channel);
1134
	else if (hal->ah_radio == AR5K_AR2425)
1135
		ret = ar5k_ar2425_channel(hal, channel);
1132 1136
	else
1133 1137
		ret = ar5k_ar5112_channel(hal, channel);
1134 1138

  
......
1251 1255
	u_int16_t c;
1252 1256

  
1253 1257
	data = data0 = data1 = data2 = 0;
1254
	c = channel->c_channel + hal->ah_chanoff;
1258
	c = channel->c_channel;
1255 1259

  
1256
	/*
1257
	 * Set the channel on the AR5112 or newer
1258
	 */
1259 1260
	if (c < 4800) {
1260 1261
		if (!((c - 2224) % 5)) {
1261 1262
			data0 = ((2 * (c - 704)) - 3040) / 10;
......
1267 1268
			return (AH_FALSE);
1268 1269

  
1269 1270
		data0 = ar5k_bitswap((data0 << 2) & 0xff, 8);
1270
	} else {
1271
	} else if ((c - (c % 5)) != 2 || c > 5435) {
1271 1272
		if (!(c % 20) && c >= 5120) {
1272 1273
			data0 = ar5k_bitswap(((c - 4800) / 20 << 2), 8);
1273 1274
			data2 = ar5k_bitswap(3, 2);
......
1279 1280
			data2 = ar5k_bitswap(1, 2);
1280 1281
		} else
1281 1282
			return (AH_FALSE);
1283
	} else {
1284
		data0 = ar5k_bitswap((10 * (c - 2) - 4800) / 25 + 1, 8);
1285
		data2 = ar5k_bitswap(0, 2);
1282 1286
	}
1283 1287

  
1284 1288
	data = (data0 << 4) | (data1 << 1) | (data2 << 2) | 0x1001;
1289

  
1290
	AR5K_PHY_WRITE(0x27, data & 0xff);
1291
	AR5K_PHY_WRITE(0x36, (data >> 8) & 0x7f);
1292

  
1293
	return (AH_TRUE);
1294
}
1295

  
1296
HAL_BOOL
1297
ar5k_ar2425_channel(struct ath_hal *hal, HAL_CHANNEL *channel)
1298
{
1299
	u_int32_t data, data0, data2;
1300
	u_int16_t c;
1301

  
1302
	data = data0 = data2 = 0;
1303
	c = channel->c_channel;
1304

  
1305
	if (c < 4800) {
1306
		data0 = ar5k_bitswap((c - 2272), 8);
1307
		data2 = 0;
1308
	/* ? 5GHz ? */
1309
	} else if ((c - (c % 5)) != 2 || c > 5435) {
1310
		if (!(c % 20) && c < 5120)
1311
			data0 = ar5k_bitswap(((c - 4800) / 20 << 2), 8);
1312
		else if (!(c % 10))
1313
			data0 = ar5k_bitswap(((c - 4800) / 10 << 1), 8);
1314
		else if (!(c % 5))
1315
			data0 = ar5k_bitswap((c - 4800) / 5, 8);
1316
		else
1317
			return (AH_FALSE);
1318
		data2 = ar5k_bitswap(1, 2);
1319
	} else {
1320
		data0 = ar5k_bitswap((10 * (c - 2) - 4800) / 25 + 1, 8);
1321
		data2 = ar5k_bitswap(0, 2);
1322
	}
1323

  
1324
	data = (data0 << 4) | data2 << 2 | 0x1001;
1285 1325

  
1286 1326
	AR5K_PHY_WRITE(0x27, data & 0xff);
1287 1327
	AR5K_PHY_WRITE(0x36, (data >> 8) & 0x7f);
ar5xxx.h 10 Jul 2014 20:49:40 -0000
1113 1113
	HAL_BOOL		ah_pci_express;
1114 1114
	HAL_RFGAIN		ah_rf_gain;
1115 1115

  
1116
	int			ah_chanoff;
1117

  
1118 1116
	HAL_RATE_TABLE		ah_rt_11a;
1119 1117
	HAL_RATE_TABLE		ah_rt_11b;
1120 1118
	HAL_RATE_TABLE		ah_rt_11g;